In the advance bulk CMOS technology (e.g., 40 nm and below), current leakage appears more and more significant. When the operating frequency is low (e.g., the corresponding device is running slow), the current leakage becomes dominant in total power consumption. To reduce total power consumption, one method reduces current leakage during standby mode, but fails to reduce leakage during normal operation. Conventional dual rail memory designs reduce the bit array leakage power during the memory standby or sleep mode, but, in various approaches, require an additional pin to select the power switches. These approaches also need long wake-up time before returning to the normal operating mode.
Like reference symbols in the various drawings indicate like elements.